xe2x80x9cSet-up timexe2x80x9d and xe2x80x9chold timexe2x80x9d describe the timing requirements on the data input of a sequential logic element, such as a flip-flop or register, with respect to a clock input. The set-up and hold times define a window of time during which data must be stable to guarantee predictable performance over a full range of operating conditions and manufacturing tolerances.
FIG. 1 illustrates three clock-to-data timing relationships used to describe the relationships between setup time, hold time, and a clock edge. Referring to the first example, the set-up time SUT is the length of time that data must be available and stable before the arrival of a clock edge 100. The hold time HT is the length of time that data to be clocked into the logic element must remain stable after the arrival of clock edge 100. Set-up times limit the maximum clock rate of a system. Positive hold times can cause malfunctioning at any clock rate. Thus, chip designers strive to provide zero or negative hold-time requirements.
The second example in FIG. 1 illustrates the input and output signals of a flip-flop that meets a zero-hold-time requirement. The data, a logic one at the onset of rising edge 110, propagates through the selected logic element to raise the output signal OUT to a logic one. The third example illustrates the input and output signals of a flip-flop that fails to meet a zero-hold-time requirement. The data, a logic one at the onset of rising edge 120, does not initiate the requisite logic one output signal OUT.
The time required for the output of a sequential logic element to change states in response to a clock is termed the xe2x80x9cclock-to-outxe2x80x9d delay. When two systems (e.g., two ICs) communicate synchronously, the data source must guarantee a minimum clock-to-out delay if the receiving device has a positive hold-time requirement. IC manufacturers prefer to provide short clock-to-out delays, but may be unable or unwilling to guarantee some minimum clock-to-out delay to compensate for a positive hold-time requirement. Any input hold time requirement is, therefore, an invitation to system failure. For a more detailed discussion of clock-to-out delays, including methods of measuring them, see U.S. Pat. No. 6,233,205 to Wells et al., which is incorporated herein by reference.
FIG. 2 illustrates a conventional programmable input block 200 that addresses potential hold-time problems. (Input block 200 is part of an input/output block on a Xilinx XC4000 field-programmable gate array.) Input block 200 includes an input buffer 205, a programmable delay circuit 210, a sequential logic element 215, and three programmable multiplexers 220, 225, and 230. A programmable multiplexer 240 within delay circuit 210 can be programmed to insert none, one or both of delay elements 235 into the incoming data path to compensate for clock delays induced by relatively long signal paths in the clock distribution network. Multiplexer 230 includes both inverting and non-inverting inputs, allowing logic element 215 to clock on either positive or negative clock edges.
FIG. 3 depicts a conventional test configuration 300 for ensuring that a selected sequential storage element on a programmable logic device meets a zero-hold-time requirement. System 300 includes a conventional tester 305 connected to a field-programmable gate array (FPGA) 310. FPGA 310 is a well-known type of programmable logic device, and might be one of the Spartan(trademark) or Virtex(trademark) series of FPGAs available from Xilinx, Inc., of San Jose, Calif. FPGA 310 includes an array of configurable logic blocks 311, or CLBS, that are programmably interconnected to each other and to programmable input/output blocks 312 (IOBs). This collection of configurable logic may be customized by loading configuration data into internal configuration memory cells that define how the CLBS, interconnections, and IOBs are configured. FPGA 310 additionally includes a clock distribution network 313 that can be connected to an external clock source (not shown) via eight global clock buffers 314 located in the four corners of FPGA 310. Each global clock buffer 314 has a corresponding pass transistor for gating an external clock signal to the input terminal of the respective clock buffer. For example, a pass transistor 315 selectively gates the signal on an input pin 325 through one of clock buffers 314 to clock distribution network 313. The signal on input pin 325 is additionally available to IOB 312B.
Clock distribution network 313 can be programmably connected to any of CLBs 311 or IOBs 312. In the depicted example, clock distribution network 313 connects input pin 325 to an input terminal of IOB 312A.
Tester 305 includes a pair of output leads 317 and 320 connected to respective input/output pins 325 and 330 of FPGA 310. Tester 305 also includes an input line 335 connected to an input/output pin 340 of FPGA 310. Tester 305 simultaneously applies input signals to pins 325 and 330 and monitors the output signal on line 335 to determine whether the correct data on line 320 clocks into IOB 312A. An incorrect logic level on line 335 indicates a hold-time violation.
Conventional test configuration 300 fails to provide acceptable levels of accuracy because tester 305 is typically too imprecise to effectively measure set-up and hold times. For example, while tester 305 may be able to place edges with nanosecond precision, set-up and hold times in leading-edge processes can be much shorter, e.g. a few tenths of a nanosecond.
Systems and methods have been proposed for quickly and accurately testing sequential logic elements on programmable logic devices for zero-hold-time compliance. See, for example, U.S. Pat. No. 6,239,611, issued to Michael M. Matera on May 29, 2001, entitled xe2x80x9cCircuit and Method for Testing Whether a Programmable Logic Device Complies With a Zero-Hold-Time Requirement,xe2x80x9d which is incorporated herein by reference. In that example, a programmable logic device is configured such that both the data and clock terminals of a selected sequential logic element connect to an input pin of the programmable logic device, and the output terminal of the sequential logic element connects to an output pin of the programmable logic device. A circuit tester connected to the input pin then generates a signal transition on the input pin so that the signal transition traverses the data and clock paths in a race to the sequential logic element. The circuit tester also includes an input terminal that monitors the PLD output pin to determine whether the logic element contains the correct data after the logic element is clocked. Incorrect data stored in the sequential logic element after the logic element is clocked indicates that the clock signal arrived too soon, and therefore that the logic element violated the zero-hold-time requirement in the specified configuration.
The above-described method is a specialized, easily implemented go/no-go test that works well to test for zero hold time compliance. However, the method does not work on all architectures, and does not provide a measure of set-up time.
The present invention is directed to a system and method for quickly and accurately measuring the timing requirements of sequential logic elements on programmable logic devices. In accordance with one embodiment, programmable interconnect resources are configured to deliver a pair of test signals to the data and clock terminals of each logic element under test. A variable delay circuit places signal edges on the clock (data) terminal a precise, known delay before or after corresponding signal edges on the data (clock) terminal. A tester then monitors the data clocked into the logic element to determine whether the logic element functions properly with the given delay. This process is continued over a number of selected delays to determine the maximum and minimum timing requirements of the element under test.
Timing requirements for a given logic element may differ depending on whether the data represents a logic zero or a logic one. Some embodiments therefore provide means of separately measuring timing requirements for clocking both rising and falling data edges using either rising or falling clock edges. Still other embodiments accurately measure clock-to-out delays of sequential logic elements.
This summary does not limit the invention, which is instead defined by whatever claims issue.